1. Field of the Invention
This invention relates to multi-bit-per-cell memory, digital recording of music and other information, and methods for using multi-bit-per-cell memory to provide the maximum data density that is consistent with data integrity requirements.
2. Description of Related Art
Multi-bit-per-cell memories can increase the density of data storage in an integrated circuit device by storing multiple bits of information in a memory cell that would store only a single bit in a conventional binary memory. One type of non-volatile multi-bit-per-cell memory contains an array of floating gate transistors, which act as memory cells. Each floating gate transistor has a threshold voltage that represents a data value stored in a memory cell. In particular, the useable range for the threshold voltage of a memory cell is divided into windows with each window being associated with a different value. A write operation sets the threshold voltage of a memory cell to a level in the window corresponding to the value being written. A read operation identifies which window contains the current threshold voltage of a memory cell and generates a signal representing the value associated with the identified window.
A conventional binary memory divides the threshold voltage range into two windows, a high threshold voltage window representing one binary value 1 or 0 and a low threshold voltage window representing the other binary value 0 or 1. A memory storing two bits per cell uses four threshold voltage windows corresponding to four values that two bits can represent. More generally, a memory storing N bits per cell uses 2N windows corresponding to all possible N-bit values. Accordingly, the number (2N) of windows increases exponentially as the number (N) of bits per cell increases, and the windows similarly decrease in width as greater numbers of windows are fit within the same available threshold voltage range.
Narrower threshold voltage windows make precise writing and reading of data more difficult. Additionally, charge leakage and other effects that change threshold voltages make preserving threshold voltages in narrow windows (i.e., preserving stored data) difficult. When the number of bits per cell becomes too large, a memory may be unable read, write, or preserve data values with the accuracy that data integrity requirements mandate. Accordingly, when data integrity requirements are high, a memory cannot store as many bits per cell and cannot achieve the storage density permitted for data that is more error tolerant.
In accordance with an aspect of the invention, a memory that is capable of storing different numbers of bits per cell uses fewer bits per cell when storing data having high data integrity requirements and uses more bits per cell when storing error-tolerant data. Accordingly, the memory can achieve both the required data integrity and high storage densities when different types of stored data have different data integrity requirements.
In accordance with one embodiment of the invention, a memory classifies portions of formatted data according to data type, where different data types need different levels of data integrity to achieve desired performance. The formatted data can be, for example, music or image data encoded according to an industry standard. The memory then stores the different types of data using different numbers of bits per cell, where the number of bits per cell for a particular portion of data depends on the data type.
In one specific embodiment of the invention, the memory includes a decoder that receives and decodes a formatted data stream and automatically designates different portions of the data stream for storage at different densities (i.e., different numbers of bits per cell). Each portion of the data structure is then stored with a number of bits per cell that provides the data integrity required for that portion. As a result, storage provides the desired performance and the maximum storage density.
Another embodiment of the invention is a multi-bit-per-cell-memory that includes: an array of non-volatile memory cells; a write circuit coupled to the array; and a decoder coupled to receive a data stream and control the write circuit to write data from the data stream into the array. During a recording operation, the decoder decodes the data stream to identify data types for portions of the data stream, and for each of the portions of the data stream, the decoder selects a number of bits written per memory cell when writing data from that portion. The number of bits per memory cell for any portion of the data stream is selected according to the data type of the portion.
Generally, the memory further includes a read circuit coupled to the array. The decoder that controls the write circuit can control the read circuit, or a second decoder can control the read circuit. During a playback operation, the decoder that controls the read circuit receives a data stream that the read circuit reads from the array. That decoder decodes the data stream to identify data types for portions of the data stream, and for each of the portions of the data stream, the decoder selects a number of bits to read from each memory cell storing that portion. The number of bits read per memory cell for any portion of the data stream is selected according to the data type of the portion.
In accordance with another aspect of the invention, the decoder or decoders in the multi-bit-per-cell memory can include programmable array logic or other similar circuitry that can be programmed or reprogrammed according to the format or protocol expected for the input or output data stream. Accordingly, the memory can adapt on-the-fly to storage of data having different formats.